The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to methods for improving overlay metrology contrast for aligning patterned features in different layers of a semiconductor device.
Semiconductor devices and integrated circuits are generally formed of multiple layers including patterned features. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed in the same layer, above the same layer, or below the same layer. Proper alignment of different layers is essential for proper performance of the fabricated semiconductor devices and circuits. For advanced design rules, overlay accuracy becomes even more difficult and important given the critical dimensions of the various features. Poor overlay signal due to the increases in the stack thicknesses needed for multilayer lithography currently used at the 10 nm and 7 nm technology nodes can have a tremendous impact on overlay error.